SoC Design Engineer

About this role

SoftQuantus is designing compute systems from the ground up. The next bottleneck in AI infrastructure is not software — it is silicon. We are exploring custom SoC architectures tailored for AI inference and quantum control workloads, where general-purpose GPUs fall short on efficiency and cost-per-operation. We are looking for a SoC Design Engineer who understands the full stack from RTL to physical implementation and can translate system-level requirements into silicon-level decisions.

Focus Areas

• •Custom AI inference accelerator architecture (NPU, tensor cores, dataflow engines)
• •SoC integration: CPU subsystems, memory controllers, NoC, PCIe, high-speed I/O
• •RTL design and verification (SystemVerilog / VHDL)
• •Physical design awareness: floorplanning, clock distribution, power domains
• •FPGA prototyping and pre-silicon validation

Responsibilities

• Define and implement RTL blocks for AI inference and control plane workloads
• Design and integrate SoC subsystems: memory interfaces, interconnects, accelerator tiles
• Develop and maintain verification environments (UVM, formal, simulation)
• Collaborate with architecture team to translate performance targets into microarchitectural specs
• Prototype designs on FPGA for early system validation
• Contribute to design reviews, timing closure analysis, and DFT planning
• Support tape-out activities and post-silicon bring-up

Requirements

• Strong experience in RTL design with SystemVerilog or VHDL
• Solid understanding of SoC architecture: CPU clusters, memory subsystems, on-chip networks
• Experience with functional verification (simulation, UVM, or formal methods)
• Familiarity with FPGA-based prototyping flows (Xilinx / Intel FPGA)
• Knowledge of synthesis and static timing analysis (STA)
• Systems-level thinking: from algorithm requirements to silicon constraints

Nice to Have

• ○Experience with RISC-V processor design or customization
• ○Background in ML accelerator architecture (systolic arrays, dataflow engines)
• ○Exposure to physical design flows (Synopsys / Cadence toolchains)
• ○Knowledge of advanced packaging (chiplets, UCIe, or HBM integration)
• ○Prior tape-out experience (TSMC, GF, or academic PDK)
• ○Familiarity with open-source EDA tools (OpenROAD, Yosys)

Skills & Keywords